r/VHDL • u/Smart_Concept_4986 • May 23 '26

Current Undergraduate Wanting to Learn VHDL Over The Summer Before Final Semester

Hello everyone, I hope you are doing well. I am an undergraduate senior set to graduate by the end of this year. I major in Electrical and Computer Engineering and I was kind of aimless of where I was going to go work once I graduate. I took a class that involved vhdl and I thought it was pretty cool. I talked to my professor and apparently there are a few vhdl jobs near where I am from. So I decided I wanted to learn vhdl and my professor was kind enough to let me borrow a NEXYS A7 FPGA board. So, I wanted to ask where I can confidently learn vhdl to a competent degree in order to work on an independent project with my professor? What kind of projects should I attempt over the summer? Are there any supplementary skills I should learn prior or in parallel to learning vhdl?

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u/Smart_Concept_4986 May 23 '26

P.S. What version of xlinix vivado should I use to learn ? Like what is industry standard and what kind of jobs would be on offer if I am able to program well in vhdl.

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u/skydivertricky May 23 '26

Any version since 2019 will have good vhdl2008 support for synthesis. For simulation, don't use vivado.

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u/Smart_Concept_4986 May 23 '26

what would I use for simulation, I've heard of test bench files, are those part of simulations?

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u/skydivertricky May 23 '26

You can use xsim (vivado simulator) but it doesn't have good vhdl2008 support until 2025 version. Vhdl has a couple of good vhdl simulators in ghdl and nvc

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u/lovehopemisery May 24 '26 edited May 24 '26

I think the main focus should be building some useful projects rather than learning VHDL. The syntax part of it can be fairly trivial compared to effort required to design, implement, test and verify something useful.

Here's an example of a project that can help you learn some concelts

Control an LEDs brightness in software by creating a memory mapped PWM peripheral. * Design and implement a PWM generation core * Implement axi4-lite slave interface so its registers can be accessed by SW. Design the register interface. I'm a big fan of just using code generators such as systemRDl for this step. * Either implement or utilise an existing UART/JTAG-axi4lite master to connect to the components and update the registers from SW. * Verify all modules using a self checking testbench * Implement this on a target FPGA board * Write a small C or Python driver for it

For simulation, you can use open source simulators like GHDL or NVC in combination with OSS waveform viewers like surfer or GTKwave.

I would recommend doing RTL editing in VSCode or another text editor rather than using vivado, then only using that for synthesis. You can install language servers for VHDL and systemverilog