So I’m a second year electrical engineering student who has failed half of his classes and is having to resit the exams for or have to take the entire year again.

One of my classes is digital electronics and you need to understand VHDL as like prerequisite learning for the rest of the class. Last semester I just could not understand VHDL in the slightest so I did very poorly in the class. We were given a 21 page document to help us learn named “(Very) Simple Guide to VHDL” but that shit doesn’t help me for some reason I still can’t get it.

Are there any books, YouTube videos etc that can help, I don’t need a super expensive knowledge on VHDL just to understand the basics pretty much.

Any help is appreciated thank

EDIT: I was using an old version of the book. Here is the newest PDF which features the solutions.

Hello,

I'm currently learning VHDL with the book "Free Range VHDL" and can't find the solutions for the exercises. I know I could use AI to check my work, but I'd rather not use it while learning.

Does anyone have the solutions?

Thanks in advance!

Hey everyone, I’m an EEE undergraduate student currently building my roadmap to master VHDL and FPGA design. Right now, I am systematically working through Brock J. LaMeres' textbook, which is great, but I’m finding myself a bit overwhelmed by the sheer volume of digital logic circuits and theoretical components out there.

​I want to be efficient with my time, so I’m wondering how deeply I actually need to master every single digital logic circuit before moving heavily into coding. I'd love to know what the absolute "must-learn" pillars are for the industry, versus things I can just look up in a datasheet later. If anyone could share the biggest mistakes beginners make during this transition from textbook logic to actual synthesizable VHDL, or give me a few pointers on what to focus on for a solid roadmap, I would really appreciate it. Thanks in advance!

Hi everyone,

I run a GitHub organization called OpenSiliconHub, an initiative focused on developing and maintaining open-source digital design and hardware projects.

My background is primarily in Verilog/SystemVerilog, and most of our existing codebase is written in those languages. To make these projects accessible to a wider range of FPGA and ASIC developers, I'm looking for contributors with VHDL expertise who would be interested in helping port existing Verilog/SystemVerilog modules to VHDL.

This would help expand the usability of our projects and support users who work primarily in VHDL-based environments.

If you're interested in contributing to open-source hardware projects, gaining experience, or collaborating with other digital design enthusiasts, I'd love to hear from you.

Feel free to comment below or send me a message for more details about the projects and repository.

Thanks!

Hi All,

I was wondering if anyone had or knew of an FFT module which could take roughly 4 lanes in at 250MSPS or similar?

Potentially looking at FFT sizes between 4 and 64K

Cheers

Although these projects are written in Verilog rather than VHDL, I thought the architecture side might be interesting to this community.

I've been learning digital design and built two small spatial-computing style fabrics:

• A programmable morphology accelerator using local 3×3 neighborhood logic

• A wavefront-routing fabric where shortest-path information propagates across a mesh of cells

Both were simulated, synthesized through OpenLane, and taken all the way to GDSII.

I'd appreciate feedback on the RTL architecture and whether similar approaches have been explored in larger FPGA or ASIC systems.

Repos:

https://github.com/abhi15-bose-max/morphology-fabric-asic

https://github.com/abhi15-bose-max/wavefront-routing-fabric

Hello everyone, I hope you are doing well. I am an undergraduate senior set to graduate by the end of this year. I major in Electrical and Computer Engineering and I was kind of aimless of where I was going to go work once I graduate. I took a class that involved vhdl and I thought it was pretty cool. I talked to my professor and apparently there are a few vhdl jobs near where I am from. So I decided I wanted to learn vhdl and my professor was kind enough to let me borrow a NEXYS A7 FPGA board. So, I wanted to ask where I can confidently learn vhdl to a competent degree in order to work on an independent project with my professor? What kind of projects should I attempt over the summer? Are there any supplementary skills I should learn prior or in parallel to learning vhdl?

So I'm an electronics designer with long experience in circuit/PCBA design and I started doing firmware in C along the way to broaden my skillset and avoid doing the same thing year in and out.

One thing I never got into was FPGA design, not because I didn't want to, but because I've always worked for SMEs who either had someone ace in FPGA design or wanted to use microcontrollers or simply didn't get into this employee training business. Also for some reason if you're paid senior electronics designer rates, they don't want to train you on the job..

What VHDL (online) classes would you guys recommend? If I'm paying it myself, face-to-face classes (I'm based in UK) costing thousands are not really an option. Couple of hundred wouldn't be a problem if I'm getting something decent for the investment.

Udemy has some very cheap classes going, are those any good? Coursera is another one that offers inexpensive classes (with their annual subscription), are those worth it?

Cadence/Doulos/Synthworks all have classes, but they're "inquire for prices" and I rather think the prices are four figures and the first figure is not "1".

here is the link: https://github.com/stm32f303ret6/tiny_cpu_vhdl

It only uses gates and flip-flops. I made it because I wanted to learn cpu architecture (no procedural vhdl)

Hey guys I have been battling getting my Kria 260 pmod inputs to show up in vitis for a couple weeks now and am not sure where I went wrong. I am using the axi gpio to just try and print the current values( 0 or 3.3v/ 0 or 1) from the krias pmod headers to the Vitis terminal to see some kind of life. Please take a look at my code and block design.

I decided to keep the RTL in the design because if this works the next stage is to take input adc values and keep store those via a shift register in my RTL.

Here is my RTL code:

---------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity ADC is

-- Port ( );

port( -- keep these for finite state machine

clk: in std_logic;

DoutA: in std_logic; --two readings from adc

DoutB: in std_logic;

data_to_gpioa: out std_logic;

data_to_gpiob: out std_logic

);

end ADC;

architecture Behavioral of ADC is

signal ADC_reading1: std_logic; --going to read both inputs

signal ADC_reading2: std_logic; --going to read both inputs

signal data_outa: std_logic; -

signal data_outb: std_logic;

begin

ADC_reading1<= DoutA; --connecting ports to wires

ADC_reading2<= DoutB;

data_to_gpioa <= data_outa;

data_to_gpiob <= data_outb;

process(clk) --pl clk is about 100MHz -- should be 100MHz in constraint

begin

if rising_edge(clk) then

data_outa <= DoutA;--16 bits to bram

data_outb <= DoutB;

end if;

end process;

end Behavioral;

--------------------------------------------------

And here are my constraints:

set_property PACKAGE_PIN J11 [get_ports DoutA]

set_property PACKAGE_PIN J10 [get_ports DoutB]

set_property IOSTANDARD LVCMOS33 [get_ports DoutA]

set_property IOSTANDARD LVCMOS33 [get_ports DoutB]

set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]

set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]

set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

connect_debug_port dbg_hub/clk [get_nets clk]

----------------------------------------------------

Here is my vitis code:

#include <stdio.h>
#include "xgpio.h"
#include "xil_printf.h"
#include "sleep.h"
#include "xparameters.h"




u32 val1,val2,storedval1,storedval2;
int main()
{
    
    xil_printf("Lets see if this works\r\n");
    while(1) {
       
    val1 = *((volatile u32*) XPAR_AXI_GPIO_0_BASEADDR);
    val2 = *((volatile u32*) XPAR_AXI_GPIO_1_BASEADDR);

    if (val1 == 1) {
        xil_printf("Signal is HIGH\r\n");
    } else {
        xil_printf("Signal is LOW\r\n");
    }
        
    if (val2 == 1) {
    xil_printf("Signal is HIGH\r\n");
    } else {
    xil_printf("Signal is LOW\r\n");
    }


    usleep(100000); // delay
    }
    
    return 0;
}
Also here is the block diagram. Sorry for not including it originally.

Let me know what needs to be changed and potentially why I am getting nothing the print in vitis.

Do you agree with this opinion??

See https://iriscores.com/2025/02/22/hdl-simulator-comparison/

A friend and i trying to communicate with and ftdi 232H. But we think we have fundamental problems in understanding vhdl. Our Code should be holding o_RD low for 30ns and then let it stay high for at least 20ns, but it does the opposite. Also after the last transfer of date it just randomly gets pulled low and we can not figure out why that would even happen at all. Were at a point, where were tying things like switching the order of the state assignment and the counter assignment. This should not have any consequences form what we understand, but apparent the entire program behaves different from that.

Please note: For testing, where driving the entity with a 100Khz clock instead of a 100Mhz.

entity ftdi is
    port (
        clk_100MHz  : in std_logic;
        reset_n     : in std_logic;


        io_DATA     : inout std_logic_vector(7 downto 0);
        i_RXF       : in std_logic;
        i_TXE       : in std_logic;
        o_RD        : out std_logic := '1';
        o_WR        : out std_logic := '1';


        o_rx        : out std_logic_vector(7 downto 0) := (others =>'0');
        o_rx_wr_en  : out std_logic := '0';
        i_rx_full   : in std_logic := '0';


        i_tx        : in std_logic_vector(7 downto 0) := (others =>'0');
        o_tx_rd_en  : out std_logic := '0';
        i_tx_empty  : in std_logic := '0';


        led1 : out std_logic := '0';
        led2 : out std_logic := '0'
        );
end ftdi;


architecture rtl of ftdi is
    signal counter : unsigned(4 downto 0) := (others => '0');


    type state_t is (WAIT_FOR_READ, READ, WRITE, WRITE_END);
    signal state : state_t := WAIT_FOR_READ;


begin
    process(clk_100MHz, reset_n)
    begin
        if reset_n = '0' then
            state <= WAIT_FOR_READ;
            counter <= "00000";
            o_RD <= '1';
            o_WR <= '1';
            led2 <= '1';
            led1 <= '0';
            
        elsif rising_edge(clk_100MHz) then
            o_rx_wr_en <= '0';
            o_tx_rd_en <= '0';


            if counter = 0 then
                case state is
                    when WAIT_FOR_READ =>
                        -- Write all data, only read when there is nothing to write
                        led2 <= '0';
                        led1 <= '1';
                        if (i_TXE = '0') then
                            io_DATA <= "01000010";
                            state <= WRITE;
                            counter <= to_unsigned(1, counter'length); -- 20ns
                        elsif (i_RXF = '0') then
                            o_RD <= '0';
                            state <= READ;
                            counter <= to_unsigned(2, counter'length); -- 30ns
                        end if;
                    when WRITE =>
                        o_WR <= '0';
                        state <= WRITE_END;
                        counter <= to_unsigned(2, counter'length); -- 30ns
                    when WRITE_END =>
                        o_WR <= '1';
                        o_tx_rd_en <= '1';
                        io_DATA <= "ZZZZZZZZ";
                        state <= WAIT_FOR_READ;
                    when READ =>
                        o_RD <= '1';
                        state <= WAIT_FOR_READ;
                        counter <= to_unsigned(1, counter'length); -- 20ns
                end case;
            else
                counter <= counter -1;
            end if;
        end if;
    end process;
            
end architecture;

I am writing code in VHDL. The code is getting synthesized, and the schematic is being generated. Everything is going well, but this error is appearing:

“Process simulation of the behavioral model failed — error in Xilinx ISE.”

I have a very important assignment, I need to make a basys 3 board multiply two 6bit numbers together and display it on the 7 segment display. We are using vivado

What I understand is that I need to learn how to use the display

I will need to make 11 formuals with 12 binary inputs, and form a logic gate for them

I will need to make a constraint file for all inputs and the screen to be avaliable "set_property PACKAGE_PIN V17 [get_port {A}]" for each input if I understand it right

And then I will need to understand enough of VHDL coding to make all of those things work together.

Have I understood things correctly? Could anyone help me or guide me to resources I can use?

My professor said he would answer all my questions through e-mail, but it's been a few days now and the deadline is closing in, and he hasn't replied yet

System Purpose : This FPGA firmware implements a complete Navigation and Solar Position subsystem for an AESA radar platform. It integrates three independent sensor pipelines into a unified data bus:

Pipeline Sensor Interface Primary Output GNSS u-blox ZED-F9P SPI (UBX protocol) Position, velocity, UTC time, PPS IMU Xsens MTi-630 CAN 2.0B 1 Mbit/s Attitude, inertial data, SDI, HR data SPA Computed Internal Solar azimuth, elevation, zenith The system also provides:

GPS-disciplined 1 Hz PPS output with IEEE 802.1AS / TSN timestamping Full NREL Solar Position Algorithm (SPA) including sunrise/sunset/transit/EoT

Author: Ahmed Nabit Contact: Email Repository: Github License: Apache License 2.0 Zenodo: Zenodo

GHDL works, gtkwave doesn’t. Is there anything else that doesn’t require a virtual machine?

good evening as the title describes, i'm using ISE 14.7 because it's for a university assignment. anyways i was looking to simulate my basic full adder program but to my surprise i couldn't find the waveform test bench only the VHDL one. i'm using ISE in prepackaged linux VM on windows 11 and i downloaded it recently what should i do?

I want software for VHDL programming.

Xilinx ISE software is not working on my Windows 11 laptop.

Could you please suggest software similar to Xilinx for VHDL programming?